Scientists at Google Research describe a new learning-based approach for chip design that learns from past experiences, improves over time, and therefore completes chip designs in under six hours on average.
Significantly faster than it takes human experts, the technique could help startups develop their chips for AI once the work is made publicly available. Additionally, we’re expecting a shorter chip design cycle that can pave the way for adapting-hardware – one that can cope with evolving research.
“Basically, right now in the design process, you have design tools that can help do some layout, but you have human placement, and routing experts work with those design tools to kind of iterate many, many times over,” Google AI lead Jeff Dean told VentureBeat in an interview late last year. “It’s a multi-week process to actually go from the design you want to actually having it physically laid out on a chip with the right constraints in area and power and wire length and meeting all the design roles or whatever fabrication process you’re doing,” said Dean.
The approach focuses on placing a netlist of logic gates and memory onto a chip canvas while keeping in mind the placement density and routing congestion.
The AI framework aids an agent, trained through reinforcement learning, with chip placements. With an empty chip, the agent places the components until it completes the netlist. These components are sorted by descending size to guide the agent in selecting which ones to put first.
A data set of 10,000 chip placements were required to train the agent. The more chips trained, the faster the training process became and the higher the quality of the results.
“We can essentially have a machine learning model that learns to play the game of [component] placement for a particular chip,” concluded Dean.
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